With an increase in the capacity of the semiconductor memory device, memory devices of multibit (e.g., .times.16 or .times.32 bits) construction have been required more and more. Further, the memory devices provided with a serial access function have been increased in order to increase the data input/output speed.
In particular, where image data are handled, a high speed serial access memory device is indispensable. Accordingly, in the memory device, such a construction that data are first transferred simultaneously in parallel and then outputted in series has been adopted recently. This method has been developed to transfer data at high speed by providing a parallel-serial transforming circuit in the data input/output sections. Therefore, in the case of a field memory or a video RAM, registers are provided to store data for one row of the cell array simultaneously and then output the stored data in series.
On the other hand, with the advance of the memory capacity and the number of bits (multibit), such a construction has been adopted that the memory cells are divided into a number of memory cell arrays and further object memory cells are further selected from a selected memory cell array, in order to decrease the power consumption and increase the data transfer speed. In particular, in the case of the dynamic type memory cells, since minute cell data must be sensed and further amplified, it is indispensable to divide the cell array into cell groups within a data sensible range. In the memory device constructed as described above, when the serial read function is required, it is necessary to provide registers for parallel-serial transformation for each cell array.
FIG. 5 shows a general memory construction of a 4M video RAM of 256 k.times.16 cells, by way of example. In this memory device, each cell array is composed of 128 kbit cells. In FIG. 5, regions B show the register sections for parallel-serial transformation, and each register section is composed of 256 bit registers. On the other hand, each cell array region C includes mechanisms (e.g., sense amplifiers) for access to cell information. As understood by the comparison between the regions C and the regions B in FIG. 5, the ratio of the chip area occupied by the regions B including the parallel-serial transforming sections to the total chip area is fairly large.
Further, FIG. 6 shows a register for one column (which corresponds to an area A in FIG. 5). As shown in FIG. 6, a word line pair WL(A) and WL(B) connected to a memory cell pair MC is connected to a sense amplifier SA via two bit lines B and /B. Further, the sense amplifier SA is connected to serial register SR through transfer gates TG. To the serial register SR, a high potential supply voltage Vcc and a low potential supply voltage Vss are both supplied. Further, the serial register SR is connected to a data line pair DQ and /DQ via select gates SG. The transfer gates TG are controllably turned on or off in response to a transfer gate signal X'fer G, and the select gates SG are controllably turned on or off in response to a gate select signal SL.
The operation of the above-mentioned register will be described hereinbelow.
When any of the word line WL(A) or WL(B) is activated, data of the memory cell pair MC is developed on the bit line pair B or/B. A small potential difference based upon the cell data is amplified by the sense amplifier SA. The above operation is executed in common for both the data refresh of the memory cell MC and the data read on the object word line WL(A) or WL(B).
Here, in a command cycle for transferring the read data to the serial register SR in parallel, after the sensing operation by the sense amplifier SA ends, the sensed data is transferred to the serial register SR. In other words, after the potentials of the bit line pair B and/B have been sensed sufficiently by the sense amplifier SA, the transfer gate signal X'fer G rises to open the transfer gates TG, so that the content of the serial register SR is written to the data of the sense amplifier SA. This rewrite operation is executed at the same time in all the 256-bit registers (in all the rows).
After the data have been written to the serial registers SR, the transfer gates TG are closed. After that, the select gates SG connected between the serial register SR and the data line pair DQ and/DQ are opened one by one on the basis of the gate select signal SG, so that data can be transferred to the outside in series through the data line pair DQ and/DQ.
Further, the serial register SR is of CMOS flip-flop, which can hold the data until the high potential supply voltage Vcc and the low potential supply voltage Vss are both once turned off.
FIG. 7 shows a circuit functional block for realizing the above-mentioned operation.
In FIG. 7, a word line control block WL CTL selects the word line WL(A) or WL(B) and controls the sense operation of the cell array CA.
Here, the selected word line WL(A) or WL(B) is any one of the word line which correspond to the data-read row in the case of the data transfer command cycle, and any one of the word line obtained when all the word line WL(A) and WL(B) are selected cyclically at a predetermined sequence in the case of the refresh command cycle.
Further, the transfer gate control block X'fer CTL gives a word line address to be transferred to the word line control block WL CTL in the transfer command cycle, so that data of the cell array CA (whose address is designated) can be sensed by the sense amplifier SA via the word line WL(A) and WL(B) and the bit line pair B or/B. Further, the data sensed by the sense amplifier SA is transferred to the serial register SR (as the parallel-serial transforming circuit) by applying the transfer gate signal X'fer G to the transfer gates TG.
On the other hand, the refresh control block Ref CTL generates an address at predetermined sequence to refresh the dynamic cell array CA in sequence, and transmits the generated address to the word line corresponding to the designated address, so that the memory cell can be refreshed through the word line sensing operation.
In the conventional memory device constructed as described above, however, there exists a problem in that the ratio of area occupied by the serial registers to the total chip area becomes relatively large. In other words, even in the case where the serial registers are added to the general-purpose DRAM to form a field memory or an image memory, it is of course necessary to suppress the area occupied by the serial registers as small as possible, that is, it is one of the important factors to reduced the chip area for reduction of the manufacturing cost of the memory device. This is because where the serial registers are added to the DRAM, if the chip areas occupied by the registers increases excessively beyond some extent, the cost of the memory device provided with the serial registers increases beyond that of the general-purpose DRAM. Therefore, conventionally, in the case where the serial registers used to read data in series are additionally incorporated in the ordinary DRAM, there exists a problem in that it has been difficult to suppress an increase of the chip area occupied by the serial registers, that is, to reduce the manufacturing cost of the memory chip.